Richard E. Hessel
26Patents
22h-index
56Co-inventors
84Inventor score
Filing activity: Jun 11, 1990 → May 29, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5179702A | System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling | Physics | 448 | Expired |
| US8356144B2 | Vector processor system | Physics | 410 | Active |
| US6195676A | Method and apparatus for user side scheduling in a multiprocessor operating system program that implements distributive scheduling of processes | Physics | 323 | Expired |
| US6597363B1 | Graphics processor with deferred shading | Physics | 202 | Expired |
| US6717576B1 | Deferred shading graphics pipeline processor having advanced features | Physics | 198 | Expired |
| US6614444B1 | Apparatus and method for fragment operations in a 3D-graphics pipeline | Physics | 156 | Expired |
| US6229553A | Deferred shading graphics pipeline processor | Physics | 154 | Expired |
| US6288730A | Method and apparatus for generating texture | Physics | 136 | Expired |
| US6525737B1 | Graphics processor with pipeline state storage and retrieval | Physics | 124 | Expired |
| US6577317B1 | Apparatus and method for geometry operations in a 3D-graphics pipeline | Physics | 96 | Expired |
| US6268875A | Deferred shading graphics pipeline processor | Physics | 91 | Expired |
| US6476807B1 | Method and apparatus for performing conservative hidden surface removal in a graphics processor with deferred shading | Physics | 86 | Expired |
| US7167181B2 | Deferred shading graphics pipeline processor having advanced features | Physics | 85 | Expired |
| US5208914A | Method and apparatus for non-sequential resource access | Physics | 74 | Expired |
| US6552723B1 | System, apparatus and method for spatially sorting image data in a three-dimensional graphics pipeline | Physics | 67 | Expired |
| US6771264B1 | Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor | Physics | 66 | Expired |
| US6693639B2 | Graphics processor with pipeline state storage and retrieval | Physics | 56 | Expired |
| US5381536A | Method and apparatus for separate mark and wait instructions for processors having multiple memory ports | Physics | 51 | Expired |
| US7808503B2 | Deferred shading graphics pipeline processor having advanced features | Physics | 50 | Active |
| US6577305B1 | Apparatus and method for performing setup operations in a 3-D graphics pipeline using unified primitive descriptors | Physics | 35 | Expired |
| US6664959B2 | Method and apparatus for culling in a graphics processor with deferred shading | Physics | 33 | Expired |
| US5499356A | Method and apparatus for a multiprocessor resource lockout instruction | Physics | 27 | Expired |
| US5165038A | Global registers for a multiprocessor system | Physics | 19 | Expired |
| US7543119B2 | Vector processor | Physics | 13 | Active |
| US5524255A | Method and apparatus for accessing global registers in a multiprocessor system | Physics | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.