High-density erasable programmable logic device architecture using multiplexer interconnections

US5384499A · kind A · utility

Assignee

• Altera Corporation · US

Inventors

• Bruce B. Pedersen · Sunnyvale, US
• David Chiang · Saratoga, US
• Francis B. Heile · Santa Clara, US
• Cameron McClintock · Mountain View, US
• Hock C. So · Redwood City, US
• James A. Watson · Santa Clara, US

Key dates

• Filing date: Sep 17, 1993
• Grant date: Jan 24, 1995
• Expiry date: Sep 17, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/17792
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.