Coincident activation of pass transistors in a random access memory
US5384730A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 1994 |
| Grant date | Jan 24, 1995 |
| Priority date | — |
| Expiry date | Mar 23, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The pass transistors in a random access memory array are activated only upon coincident (simultaneous) selection of both the associated row and the associated column of the memory cell; otherwise, activation of the pass transistors is prevented. Thus, when a word line is selected, only the pass transistors in the memory cell corresponding to a simultaneously selected bit line is active, rather than all of the pass transistors pairs connected to the word line. Transient power consumption during word line selection and deselection is thereby reduced. Coincident pass transistor activation may be obtained by providing a column select line for each column of the memory array, and gating means in each cell which electrically activates the associated pass transistors only upon simultaneous selection of the associated column select line and the associated word line, and for preventing activation of the associated pass transistors otherwise. When the column select lines and gating means are used, shared bit lines may be provided in the array. A single shared bit line may be used between adjacent columns of cells since only one of the columns will be selected by the column select line. A hig…
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