Data output buffer of a semiconductor memory device
US5384735A · kind A · utility
48Cited by
2References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1993 |
| Grant date | Jan 24, 1995 |
| Priority date | — |
| Expiry date | Oct 4, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device using a clock of a constant period supplied from the exterior of a memory chip and a sense amplifier for reading out data from a memory cell designated by an address includes at least two different delay circuits for setting at least two delay time periods from the clock, a selecting circuit for receiving signals generated from the delay circuits and selecting one of said signals by a given control signal, and a data output buffer for receiving the data generated from the sense amplifier by a signal generated from the selecting circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.