Churoo Park
14Patents
10h-index
12Co-inventors
61Inventor score
Filing activity: Oct 4, 1993 → Sep 18, 1998
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5568445A | Synchronous semiconductor memory device with a write latency control function | Physics | 82 | Expired |
| US5933379A | Method and circuit for testing a semiconductor memory device operating at high frequency | Physics | 65 | Expired |
| US5631871A | System for selecting one of a plurality of memory banks for use in an active cycle and all other banks for an inactive precharge cycle | Physics | 64 | Expired |
| US5590086A | Semiconductor memory having a plurality of I/O buses | Physics | 59 | Expired |
| US5835956A | Synchronous dram having a plurality of latency modes | Physics | 54 | Expired |
| US5838990A | Circuit in a semiconductor memory for programming operation modes of the memory | Physics | 51 | Expired |
| US5384735A | Data output buffer of a semiconductor memory device | Physics | 48 | Expired |
| US5621691A | Column redundancy circuit and method of semiconductor memory device | Physics | 45 | Expired |
| US5703828A | Semiconductor memory | Physics | 40 | Expired |
| US6343036B1 | Multi-bank dynamic random access memory devices having all bank precharge capability | Physics | 20 | Expired |
| US5835446A | Column decoder for semiconductor memory device with prefetch scheme | Physics | 10 | Expired |
| US5579280A | Semiconductor memory device and method for gating the columns thereof | Physics | 8 | Expired |
| US5822270A | Circuit for generating internal column address suitable for burst mode | Physics | 2 | Expired |
| US5748639A | Multi-bit test circuits for integrated circuit memory devices and related methods | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.