Method and apparatus for a bus transceiver incorporating a high speed binary data transfer mode with a ternary control transfer mode having a full duplex, dominant logic transmission scheme
US5384769A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1993 |
| Grant date | Jan 24, 1995 |
| Priority date | — |
| Expiry date | Mar 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/4135
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfer of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. The ternary receiver comprises two binary receivers for detecting resultant current amplitudes created on the bus during simultaneous driving of control signals by the nodes during the control transfer phase…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.