Programmable high speed array clock generator circuit for array built-in self test memory chips
US5386392A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1994 |
| Grant date | Jan 31, 1995 |
| Priority date | — |
| Expiry date | Jun 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit incorporating at least a SRAM that includes memory, a data-out shift register, an ABIST data compression circuit, a fail address register and an array clock generator (ACG), the ACG comprising a clock chopper that comprises a first AND gate having an inherent delay DEL1, a first input for receiving a D clock signal, a second input for receiving the D signal inverted by an invertor having an inherent delay DEL2, and an output that generates an ungated LSSSD C clock signal; and a second AND gate having an inherent delay DEL4, a first input connected to the output of an inverter having an inherent delay DEL3, the inverter is coupled to the invertor having the delay DEL2, a second input is controlled by the D clock signal and an output for generating LSSD clock signals B and S.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.