Hole capacitor for dram cell and a fabrication method thereof
US5387531A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1992 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Sep 9, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
Abstract
A method for making a hole capacitor for DRAM cell includes the steps of: depositing a nitride layer and a lower oxide layer, and forming a buried contact hole, after forming a MOS transistor upon a semiconductor substrate. Thereafter depositing an in-situ doped non-crystalline silicon layer, an undoped non-crystalline silicon layer, and a hemispherical polysilicon layer in all in sequence with a thickness of 1500 .ANG. or over. An upper oxide film is deposited, and then, carrying out an etch-back on the upper oxide film so that the hemispherical polysilicon domes are exposed. Etching the polysilicon layers using the remained portions of the upper oxide film remaining on the valleys of the hemispherical polysilicon as a mask, in order to form a plurality of holes perforated from the domes to the insulating layer located under the layers. The upper oxide film is removed through an etch process. Patterning a lower electrode of the capacitor, etching the lower oxide film, forming a dielectric layer on the surface of the lower electrode, and forming an upper electrode in match with the lower electrode across the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.