Content addressable memory device and a method of disabling a coincidence word thereof
US5388066A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1993 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Jul 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storing circuit including memory cells arranged in a plurality of rows and columns and flag cells corresponding to respective rows for storing flag information, the memory cells and the flag cell of the same row constituting one word, is provided. When a retrieval data is externally applied, the data included in the retrieval data is compared with the data of the memory cell, and the flag information stored in the retrieval data is compared with the flag stored in the flag cell. Respective results of comparison are output to a match line. Logical operation circuit carries out logical operation dependent on the result of comparison output to the match line, and writes the logical output to the flag cell of the data storing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.