Bit line switch array for electronic computer memory
US5388072A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1992 |
| Grant date | Feb 7, 1995 |
| Priority date | — |
| Expiry date | Apr 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory having rows of memory cells, each row having at least first and second blocks of memory cells. Each memory cell stores a data signal, has at least one word line input, and at least one bit line input/output. A word line connects the word line inputs of at least first, second, third, and fourth memory cells in a row of the cache memory. The first and third memory cells are contained in the first block, while the second and fourth memory cells are contained in the second block. First and second sense amplifiers or write drivers are provided for reading data from or writing data to memory cells. First and second switches having control inputs connect the bit line inputs/outputs of the first and second memory cells, respectively, to the first sense amplifier/write driver. Third and fourth switches having control inputs switchably connect the bit line inputs/outputs of the third and fourth memory cells, respectively, to the second sense amplifier/write driver. The control inputs of the first, second, third, and fourth switches are capable of being independently actuated. Selection means, such as an address decoder, independently actuate either the first and third switches…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.