Richard E. Matick
27Patents
15h-index
14Co-inventors
78Inventor score
Filing activity: Nov 29, 1976 → Dec 2, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5895487A | Integrated processing and L2 DRAM cache | Emerging Cross-Sectional Technologies | 127 | Expired |
| US4577293A | Distributed, on-chip cache | Physics | 108 | Expired |
| US4667305A | Circuits for accessing a variable width data bus with a variable width data field | Physics | 91 | Expired |
| US4905188A | Functional cache memory chip architecture for improved cache access | Physics | 74 | Expired |
| US4649516A | Dynamic row buffer circuit for DRAM | Physics | 65 | Expired |
| US4541075A | Random access memory having a second input/output port | Physics | 59 | Expired |
| US4084230A | Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control | Physics | 43 | Expired |
| US4589092A | Data buffer having separate lock bit storage array | Physics | 34 | Expired |
| US4616310A | Communicating random access memory | Physics | 34 | Expired |
| US5388072A | Bit line switch array for electronic computer memory | Physics | 28 | Expired |
| US4287575A | High speed high density, multi-port random access memory cell | Physics | 19 | Expired |
| US4663729A | Display architecture having variable data width | Physics | 17 | Expired |
| US7499312B2 | Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line | Physics | 17 | Active |
| US7133971B2 | Cache with selective least frequently used or most frequently used cache line replacement | Emerging Cross-Sectional Technologies | 17 | Expired |
| US6081872A | Cache reloading performance improvement through the use of early select techniques with and without pipelining | Physics | 15 | Expired |
| US6981096B1 | Mapping and logic for combining L1 and L2 directories and/or arrays | Physics | 13 | Expired |
| US7289369B2 | DRAM hierarchical data path | Physics | 8 | Expired |
| US7460387B2 | eDRAM hierarchical differential sense amp | Physics | 7 | Active |
| US7821858B2 | eDRAM hierarchical differential sense AMP | Physics | 5 | Active |
| US5870108A | Information handling system including mapping of graphics display data to a video buffer for fast updation of graphic primitives | Physics | 3 | Expired |
| US7471546B2 | Hierarchical six-transistor SRAM | Physics | 3 | Active |
| US7958311B2 | Cache line replacement techniques allowing choice of LFU or MFU cache line replacement | Emerging Cross-Sectional Technologies | 2 | Active |
| US7709299B2 | Hierarchical 2T-DRAM with self-timed sensing | Emerging Cross-Sectional Technologies | 1 | Active |
| US5890215A | Electronic computer memory system having multiple width, high speed communication buffer | Physics | 0 | Expired |
| US7398357B1 | Cache line replacement techniques allowing choice of LFU or MFU cache line replacement | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.