Selective recrystallization to reduce P-channel transistor leakage in silicon-on-sapphire CMOS radiation hardened integrated circuits
US5391903A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Dec 21, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/921
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon layer formed atop a sapphire substrate is selectively recrystallized such that the original degraded quality of the crystallinity of an N-well region where a P-channel device is to be formed is enhanced, so that leakage in the P-channel device is reduced, while the high ultraviolet reflectance number of a P-well region where an N-channel device resides remains unaffected. The process according to the present invention involves implanting silicon into only that portion of the silicon layer where an N-conductivity well region for a P-channel device is to be formed. An N-conductivity type impurity is introduced into the silicon-implanted portion of the silicon layer, to form the N-conductivity well region. The structure is then annealed at a relatively low temperature for several minutes, which is sufficient to activate the phosphorus and to cause local recrystallization of the N-well region of the silicon layer, without essentially causing a redistribution of the phosphorus. What results is a precisely tailored, low leakage P-channel device with a very close to ideal characteristic, integrated in the same SOS structure with a high UVR-based N-channel device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.