Result normalizer and method of operation
US5392228A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Dec 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.