Semiconductor memory circuit with block overwrite
US5392241A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multimedia dynamic random-access memory (DRAM) or video random-access memory (VRAM) having enhanced block overwrite capabilities includes a plurality of sense amplifiers which are selectively coupled to an array of memory cells via paired bit lines for sensing/writing charge to the memory cells. Each sense amplifier is controlled by a primary set device and a secondary set device. The secondary set device is of smaller size than the primary set device but still sized sufficiently to maintain accessed data appearing on the paired bit lines. Upon decoding of a block overwrite request, the primary set device is momentarily turned off to facilitate forcible overwriting of selected sense amplifiers with new data while the secondary set device maintains data appearing on unselected sense amplifiers. Once block overwrite is complete, the primary set device is reactivated and charge is restored to the memory cells. By momentarily deactivating the primary set device, block overwriting of a large number of bit line pairs is possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.