Semiconductor memory device with single data line pair shared between memory cell arrays
US5392242A · kind A · utility
13Cited by
9References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 2, 1993 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Jun 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory device has a data line pair shared between a plurality of memory cell arrays, and a column address decoder unit allows one of column selectors to couple one of the associated bit line pairs with the shared data line pair so that the data line pair is not increased together with the memory capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.