History table for prediction of virtual address translation for cache access
US5392410A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 1992 |
| Grant date | Feb 21, 1995 |
| Priority date | — |
| Expiry date | Apr 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 1-dimensional history table, which has been named a TLBLAT, is used to predict some or all of the real address bits that correspond to (i.e., translate from) any given virtual page address in order to provisionally access a real address based cache. The selection of a TLBLAT entry from given virtual address is based on certain address bits in the virtual address. The selection of a TLBLAT entry may also be based on the hashing of such virtual address bits together with other information in order to achieve sufficient randomization. At the minimum, each TLBLAT history table entry records the bits (one or more) necessary for prediction of the congruence class in a real address based cache. The set-associativity of the cache may be as low as one (i.e., a direct-mapped cache). More information may be included in each TLBLAT entry in order to facilitate various design considerations and it is possible even to combine a translation lookaside buffer (TLB) function with the TLBLAT function into a single physical table that provides the functions of both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.