Structure and method for implementing hierarchical routing pools in a programmable logic circuit
US5394033A · kind A · utility
42Cited by
3References
12Claims
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Assignee
Inventors
Key dates
| Filing date | Sep 1, 1993 |
| Grant date | Feb 28, 1995 |
| Priority date | — |
| Expiry date | Sep 1, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device has multiple groups of generic logic blocks. Each group of generic logic blocks is interconnected by a local routing pools. A global routing pool is provided to interconnect the local routing pools. The global and local routing pools can be implemented in volatile or non-volatile technology, such as E.sup.2 PROM technology. The programmable logic device can also be implemented as an in-system programmable logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.