Semiconductor integrated circuit device having a compact arrangement of SRAM cells
US5396100A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 31, 1992 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Mar 31, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.