FPGA with distributed switch matrix
US5396126A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1993 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Feb 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array (FPGA) includes a distributed switch matrix for programmably connecting the various routing conductors. The distributed switch matrix comprises groups of additional conductors, referred to as "Switching R-nodes". The Switching R-nodes programmably connect selected ones of the (e.g, horizontal) routing conductors to other selected ones of the (e.g., vertical) routing conductors. In this manner, the direct connection between the routing conductors may be avoided, allowing for a reduced number of programmable interconnect devices. In one preferred embodiment, a nibble-mode architecture is used, wherein four data conductors are provided for each group of routing conductors, with other multiples-of-four data conductors also being advantageous.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.