Low signal margin detect circuit
US5396182A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1992 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Oct 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2273
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A low signal margin detect circuit for detecting reduced signal levels in differential current switch (DCS) or current switch emitter follower (CSEF) circuits. The circuit is connected to the outputs of a DCS circuit or to the output of a current switch emitter follower circuit and a reference voltage. A signal difference between the inputs is determined and, if less than an established amount, an error signal is generated. The detect circuit is enabled by a TESTBIAS signal. Two error signals are developed, ERRORX and ERRORY, which can be dotted with the error signals from adjacent circuits in the X and Y directions. This enables detection of the failing circuit through the use of appropriate error signal detection devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.