Semiconductor neural network and operating method thereof
US5396581A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1993 |
| Grant date | Mar 7, 1995 |
| Priority date | — |
| Expiry date | Jan 19, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor neural network includes a coupling matrix having coupling elements arranged in a matrix which couple with specific coupling strengths internal data input lines to internal data output lines. The internal data output lines are divided into groups. The neural network further comprises weighting addition circuits provided corresponding to the groups of the internal data cutput lines. A weighting addition circuit includes weighing elements for adding weights to signals on the internal data output lines in the corresponding group and outputting the weighted signals, and an addition circuit for outputting a total sum of the outputs of those weighting elements. The internal data output lines are arranged to form pairs and the addition circuit has a first input terminal for receiving one weighting element output of each of the pairs in common, a second input terminal for receiving the other weighting element output of each of the pairs in common, and a sense amplifier for differentially amplifying signals at the first and second input terminals. The neural network further includes a circuit for detecting a change time of an input signal, a circuit responsive to an input sig…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.