Burn-in technologies for unpackaged integrated circuits
US5397997A · kind A · utility
214Cited by
15References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 1993 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | May 6, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device and method for burn-in of bare chips prior to assembly into a multichip module. Each die to be tested is positioned with its I/O pads positioned to face an interconnection burn-in test substrate which may be a silicon circuit board. Each die is temporarily electrically connected to the substrate by a deformable solder bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.