Microcode generation for a scalable compound instruction set machine
US5398321A · kind A · utility
21Cited by
22References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1994 |
| Grant date | Mar 14, 1995 |
| Priority date | — |
| Expiry date | Jan 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for generating microcode in a scalable compound instruction set machine operates in response to compounding information indicating that two or more adjacent instructions are to be executed in parallel. Separate and independent microcode is held in control store for each possible instruction in a group. Microcode sequences for each instruction of a group of instructions to be executed in parallel are merged in response to the compounding information into a single microinstruction sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.