Hold-type latch circuit with increased margin in the feedback timing and a memory device using same for holding parity check error
US5399912A · kind A · utility
9Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1993 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Jan 5, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hold-type latch circuit which features an increased operation margin. A feedback circuit feeds the data output logic state of a non-inversion data output terminal of the latch circuit back to a data input terminal thereof, to increase a margin in the setup time ts and holding time th in controlling the data holding capability of the latch circuit, thereby to increase the margin of thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.