Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected
US5400275A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1991 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Jun 7, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a plurality of memory cells arranged in the form of a matrix to constitute rows-and columns, a plurality of first driving lines, connected to the memory cells, for transmitting a first driving signal to the memory cells, one of the plurality of first driving lines being selected by a row address, a plurality of second driving lines, connected to the memory cells, for transmitting a second driving signal to the memory cells, one of the plurality of second driving lines being selected by a column address, a plurality of read/write lines, connected to the memory cells, for performing read/write operations with respect to the memory cells, and a plurality of sense amplifiers connected to the read/ write lines, wherein one of the plurality of sense amplifiers is selected by the column address, and the memory cells in the same column are connected to the same sense amplifier through the read/write lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.