Self-recovering erase scheme to enhance flash memory endurance
US5400286A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1993 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Aug 17, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Word line stress is used to narrow the distribution of threshold voltages after an erase of an array of memory cells. One embodiment of the invention provides a method for erasing an array including a standard erase technique followed by extra erase pulses to create a margin between threshold voltages of the cells and the erase verify level, then applying word line stress to narrow the distribution of threshold voltages. Another embodiment in addition includes verifying that all of the memory cells are still erased after applying word line stress and if any of the memory cells were over-stressed and are not erased, repeating the method but using less word line stress. The erase methods according to embodiments of the present invention can be implemented by an external CPU which executes an erase program or by circuitry embedded in an EEPROM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.