Memory cell with user-selectable logic state on power-up
US5400294A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1993 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Dec 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for forcing a memory cell to a user-selected logic level upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V.sub.CC rises from 0 volt to 3.5 volts, the PWRUP signal follows V.sub.CC and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and bit lines and V.sub.CC. During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V.sub.CC by the P-Channel pullup transistors. When V.sub.CC reaches its desired value, the PWRUP signal goes to 0 volts and the PWRUPB signal goes to V.sub.CC, thus turning on the pass gates to connect the word line and bit line driver circuits to the word lines and bit lines. The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.