All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging
US5400370A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 1993 |
| Grant date | Mar 21, 1995 |
| Priority date | — |
| Expiry date | Feb 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An all digital data algorithmic recovery method and apparatus which operates at jitter greater than 25% and where run length is more than 1000 bits and which uses self calibrated delay elements to phase align a locally generated time ruler reference with the data average transition position to reliably establish the sampling time for retrieving data from an incoming binary sequence at the center of the data eye. The phase adjusted time ruler signal is used to sample transition positions of the data and the sampled data is statistically analyzed in a state machine wherein the time ruler is a broadband signal comprising a first and second base frequency and wherein the period of one of said frequencies is ##EQU1## where F.sub.R equals the receiver local clock frequency and F.sub.T equals the frequency of the distant clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.