Variable latency scheme for synchronous memory
US5402388A · kind A · utility
49Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1993 |
| Grant date | Mar 28, 1995 |
| Priority date | — |
| Expiry date | Dec 16, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of writing or reading a semiconductor random access memory (DRAM or SRAM) having plural sense amplifiers connected to bit lines and having data bus read and write amplifiers, formed of providing a pair of data buses for access by each sense amplifier and each read and write amplifier, reading or writing one data bus while precharging the other data bus during a first read or write cycle, and reading or writing the other data bus while precharging the first data bus in a second read or write cycle following the first read or write cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.