Graham Allan
39Patents
14h-index
8Co-inventors
74Inventor score
Filing activity: Dec 10, 1993 → Dec 1, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5796673A | Delay locked loop implementation in a synchronous dynamic random access memory | Electricity | 101 | Expired |
| US6327318A | Process, voltage, temperature independent switched delay compensation scheme | Electricity | 79 | Expired |
| US6657919B2 | Delayed locked loop implementation in a synchronous dynamic random access memory | Electricity | 74 | Expired |
| US6657918B2 | Delayed locked loop implementation in a synchronous dynamic random access memory | Electricity | 72 | Expired |
| US6992950B2 | Delay locked loop implementation in a synchronous dynamic random access memory | Electricity | 71 | Expired |
| US5402388A | Variable latency scheme for synchronous memory | Physics | 49 | Expired |
| US6538911B1 | Content addressable memory with block select for power management | Physics | 41 | Expired |
| US5416743A | Databus architecture for accelerated column access in RAM | Physics | 34 | Expired |
| US6067272A | Delayed locked loop implementation in a synchronous dynamic random access memory | Electricity | 34 | Expired |
| US5973552A | Power savings technique in solid state integrated circuits | Electricity | 34 | Expired |
| US6205083A | Delayed locked loop implementation in a synchronous dynamic random access memory | Electricity | 27 | Expired |
| US6683928B2 | Process, voltage, temperature independent switched delay compensation scheme | Electricity | 20 | Expired |
| US6314052A | Delayed locked loop implementation in a synchronous dynamic random access memory | Electricity | 20 | Expired |
| US5642068A | Clock period dependent pulse generator | Electricity | 17 | Expired |
| US5729160A | Self-timed circuit control device and method | Physics | 14 | Expired |
| US7885140B2 | Clock mode determination in a memory system | Emerging Cross-Sectional Technologies | 11 | Active |
| US9384847B2 | Clock mode determination in a memory system | Emerging Cross-Sectional Technologies | 11 | Active |
| US9740407B2 | Clock mode determination in a memory system | Emerging Cross-Sectional Technologies | 10 | Active |
| US9552889B2 | Clock mode determination in a memory system | Emerging Cross-Sectional Technologies | 8 | Active |
| US7349513B2 | Process, voltage, temperature independent switched delay compensation scheme | Electricity | 7 | Expired |
| US8854915B2 | Clock mode determination in a memory system | Emerging Cross-Sectional Technologies | 7 | Active |
| US9042199B2 | Clock mode determination in a memory system | Emerging Cross-Sectional Technologies | 7 | Active |
| US7889826B2 | Process, voltage, temperature independent switched delay compensation scheme | Electricity | 6 | Active |
| US10140028B2 | Clock mode determination in a memory system | Emerging Cross-Sectional Technologies | 6 | Active |
| US5686848A | Power-up/power-down reset circuit for low voltage interval | Electricity | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.