Method for fabricating a thin film transistor
US5403755A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1993 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Oct 22, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6715
Abstract
A method for fabricating a thin film transistor using a polysilicon with a double junction structure. The method includes the steps of: PA1 forming a first insulation film, a semiconductor layer and a second insulation film on a transparent substrate, in this order; PA1 patterning the second insulation film and the semiconductor layer to remain only on a channel region; PA1 forming a first conductivity type of semiconductor layer having a low concentration and a first conductivity type of semiconductor layer having a high concentration on the whole surface, in this order, so that they are coupled to the remaining semiconductor layer; PA1 removing the first conductivity type of semiconductor layer having a low concentration and the first conductivity type of semiconductor layer having a high concentration which are located in the channel region selectively using the remaining second insulation film as an etch stopper, to define a source region and a drain region; PA1 removing the exposed portion of remaining second insulation film and then forming a gate insulation film on the whole surface; PA1 forming a gate electrode on the gate insulation film located over the channel region and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.