Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template
US5403784A · kind A · utility
61Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1993 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Jan 29, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing a pin grid array package providing a plurality of electrical input and/or output connections using a plurality of stacked, but spaced apart, separate leadframes which are preformed and include a plurality of electrical leads having first and second ends for providing a plurality of different connections. An insulating layer is positioned between adjacent leadframes and the package is bonded together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.