Pipelined multiplier for signed multiplication
US5404323A · kind A · utility
3Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1993 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Nov 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined multiplier for signed multiplication has a plurality of pipeline stages, each of which includes a row of registers, and a row of operating cells. The operating cells includes a plurality: of AND gates, NAND gates, half adders, and full adders connected to perform the signed multiplication according to the Hatamian-Cash algorithm. The pipelined multiplier is characterized by that the most significant bit of the product is directly obtained from the previous less significant bit of the product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.