Method and system for generating a bit pattern
US5404410A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1994 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Jan 10, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pattern defect inspection apparatus according to this invention comprises an irradiation circuit for irradiating a substrate on which a given pattern is drawn, a detector circuit for detecting said irradiated pattern on said substrate, a bit pattern generating circuit for quantizing and generating previously given design data by processing said design data based on specified figure information to obtain bit pattern data composed of a finite number of pixels, and a comparator circuit for detecting defects on said substrate by comparing the detected data from said detecting means with the data from said bit pattern generating means, wherein the bit pattern generating circuit has an additional parameter conditioner for setting the dimension of each pixel to be quantized into said bit pattern data to the desired value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.