Computer-based system and method for debugging a computer system implementation
US5404496A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1992 |
| Grant date | Apr 4, 1995 |
| Priority date | — |
| Expiry date | Jul 1, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synchronization of an architectural model of a computer architecture and a behavioral model of an implementation of the architecture for functional verification of the implementation. A communication channel is established between the two models through which simulation control and state information can be communicated and both models are available for simulating. Synchronization points in the models' executions are identified, and a synchronizer is implemented which instructs each model to simulate to a synchronization point and report relevant state information. The synchronizer can also verify state information from the two models in real time, flag errors, or instruct the architectural model to modify its state either to match known errors in the behavioral model or to match correct behavior to an asynchronous event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.