Method of fabricating a semiconductor memory device
US5405800A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1994 |
| Grant date | Apr 11, 1995 |
| Priority date | — |
| Expiry date | Jul 12, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
A method of fabricating a semiconductor memory device on a semiconductor substrate is disclosed. A gate electrode that becomes a word line, a bit line, and a charge-storage electrode are formed in a memory cell array region of a semiconductor substrate. A capacitor insulator layer and a plate electrode are formed in that order. Then, a BPSG film is formed in the memory cell array region and in the peripheral circuit region. A resist pattern is formed on the BPSG film, leaving the memory cell array region exposed. Using the resist pattern thus formed as a mask, an etching treatment is applied to remove an upper surface portion of the BPSG film lying within the memory cell array region by a given amount. After the resist pattern is removed, the BPSG film is heated in order that it reflows to planarize.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.