Programmable interconnect architecture using fewer storage cells than switches
US5406138A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1993 |
| Grant date | Apr 11, 1995 |
| Priority date | — |
| Expiry date | Apr 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M<N. A group of N switching elements are controlled by a group of M active storage elements, where M<N. The states of the M active storage elements are collectively decoded to identify the one of N switching elements to be turned on. A second user re-programmable interconnect architecture is provided wherein a group of N switching elements are connected between selected interconnect conductors and are partially selected by decoding the states of m.sub.1 active storage elements. The group of N switching elements are also partially selected by decoding the states of m.sub.2 active storage elements. The decoding is arranged such that the states of m.sub.1 and m.sub.2 active storage elements each are decoded to provide a partial address to identify one of the N switching elements to be turned to its "on" state. The sum of m.sub.1 and m.sub.2 is less than N. Decoder lines in non-parallel relationship with the interconnect conductors provide increased routability. P…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.