Location and standoff pins for chip on tape
US5410451A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1993 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | Dec 20, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin dielectric substrate bearing a plurality of conductive leads has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on a circuit board. The free leads are isolated from pressure applied to the chip on tape assembly after it has been connected to a circuit board by means of a thin self-supporting thermally conductive heat spreader that contacts the side of the die opposite its pads and includes fixed standoff and/or alignment pins that extend through alignment holes in the thin substrate and are in physical contact with a surface of the printed circuit board. The arrangement enables transfer of force applied to the heat spreader directly to the circuit board, thereby isolating the die, thin substrate and its fragile free leads from forces applied to the die and/or the heat spreader.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.