Asynchronous latch circuit and register
US5410550A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 1993 |
| Grant date | Apr 25, 1995 |
| Priority date | — |
| Expiry date | May 21, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An asynchronous latch circuit characterized by a pair of D-type flip-flops and a D-type latch. Data is clocked into a first flip-flop by a system clock signal and the output of the first flip-flop is clocked into a second flip-flop by an asynchronous latch enable signal. A comparator compares the outputs of the first and second flip-flops and develops an error signal if the two are not the same. The error signal forces the output of the latch to a known condition rather than letting the output be indeterminate. In an asynchronous latch register an error signal from any one of the asynchronous latch circuits will force all of the latch circuits in the register to a known condition to eliminate race condition errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.