Interconnect system for a semiconductor chip and a substrate
US5411400A · kind A · utility
35Cited by
14References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1994 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Mar 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of inserts (12) formed on a first substrate (11). A plurality of sockets (14) formed on a second substrate (13). Each socket of the plurality of sockets (14) on the second substrate (13) has a corresponding insert from the plurality of inserts (12) which physically aligns for coupling. At least one of the first (11) or second (13) substrates must be a semiconductor substrate. This arrangement allows for electrically connecting a semiconductor device or structure to another device for testing, burn-in, or final assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.