Process for improving gallium arsenide field effect transistor performance using an aluminum arsenide or an aluminum gallium arsenide buffer layer
US5411902A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1994 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Jun 6, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/357
Abstract
The incorporation of an aluminum arsenide (AlAs) buffer layer in a gallium arsenide (GaAs) field effect transistor (FET) structure is found to improve the overall device performance, particularly in the high temperature operating regime. Similar characteristics may be obtained from devices fabricated with an Al.sub.x Ga.sub.1-x As (0.2.ltoreq.x.ltoreq.1) barrier layer. At temperatures greater than 250.degree. C., the semi-insulating gallium arsenide substrate begins to conduct significant amounts of current. The highly resistive AlAs buffer layer limits this increased conduction, thus permitting device operation at temperatures where parasitic leakage currents would impede or prevent device operation. Devices fabricated with AlAs buffer layers exhibited lower drain parasitic leakage currents and showed improved output conductance characteristics at 350.degree. C. ambient temperature. The buffer layer will also improve the backgating problems which are detrimental to the operation of monolithic GaAs digital circuits having closely spaced devices under different bias conditions. An additional benefit of the high temperature capabilities of these devices is an improved reliability at …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.