Schematic compiler for a multi-format high speed multiplier
US5412591A · kind A · utility
5Cited by
11References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1990 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Aug 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplier compiler produces a schematic of a high-speed, multi-format multiplier. The compiler receives user information which indicates design preferences. Based on the user information the compiler can select the format of numbers which the multiplier will multiply and/or select a type of adder with which to implement the final adder row of the multiplier. The compiler generates user readable schematics of the multiplier. The schematic displays discrete components of the multiplier arranged in locations which show to the user the flow of logic of the circuit. Additionally, the compiler generates test vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.