Memory device having asymmetrical CAS to data input/output mapping and applications thereof
US5412613A · kind A · utility
23Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1993 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Dec 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory chip architecture is described implementing of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2.sup.n x 4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.