Adaptive data separator
US5412698A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1993 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Mar 16, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a transmission source are prefixed with two data bits of known values. The data separator is also supplied with four clock signals per bit, one corresponding to an ideal rising edge and three following every 5 nanoseconds. The two prefix bits preceding a data packet are then sampled at each of the clock signals. Since all information in a given data packet undergoes the same systematic distortion, the logic of the adaptive data separator can determine the optimum clock signal to use in sampling each bit of data for the packet. Through several multiplexers the incoming data is then clocked to the optimal clock signal for sampling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.