Process for high density split-gate memory cell for flash or EPROM
US5414287A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1994 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Apr 25, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/511
Abstract
A method and structure for manufacturing a high-density split gate memory cell, for a flash memory or EPROM, is described. Silicon islands are formed from a silicon substrate implanted with a first conductivity-imparting dopant. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over a portion of the vertical surfaces of the first dielectric layer, and acts as a floating gate for the high density split-gate memory cell. A source region is located in the silicon substrate, and is implanted with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is located in the top of the silicon islands, and is also implanted with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A second dielectric layer is formed over the top and side surfaces of the floating gate, and acts as an interpoly dielectric. A second conductive layer is formed over that remaining portion of the vertical surfaces of the first dielectric layer not covered …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.