Semi-conductor device interconnect package assembly for improved package performance
US5414299A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1993 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Sep 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device interconnect package assembly for TAB packages is disclosed having a central portion of material which is utilized as part of the package structure to provide scratch protection to the active surface of a semiconductor die and to the inner lead bonding areas. The central portion of material can be modified in various ways to improve the overall performance of the package, and to reduce stress generated in the TAB package due to thermal mismatch. The assembly also includes a plurality of apertures in the substrate film which overlap and expose a plurality of groups of inner lead portions. The plurality of apertures allows each group of exposed inner lead portions to be encapsulated independently from each other group. By encapsulating each of these groups separately, scratch protection is provided to the inner lead bonding areas while simultaneously reducing the stress on each of the leads due to the heating and cooling of the encapsulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.