Fourth-order cascaded sigma-delta modulator
US5414424A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 1993 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Aug 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/418
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for cascading three sigma-delta modulators involves applying an error signal representing the quantization error of a preceding modulator to a subsequent modulator. The error signal is scaled by a factor before being applied to a subsequent modulator. The quantized error signal of the subsequent modulator is then scaled by the reciprocal of the original scaling factor before being combined with the quantized outputs of the previous modulators. Combining the quantized outputs of the three modulators is performed so as to cancel the quantization error of the previous stages while shaping the noise at the last stage so that most of the noise is placed at high frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.