Automatic cache flush
US5414827A · kind A · utility
27Cited by
26References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 19, 1991 |
| Grant date | May 9, 1995 |
| Priority date | — |
| Expiry date | Dec 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to the invention, a chipset is provided which powers up in a default state with caching disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while caching is disabled. Even though no "valid" bit is cleared, erroneous cache hits after caching is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.