Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage
US5416048A · kind A · utility
306Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1993 |
| Grant date | May 16, 1995 |
| Priority date | — |
| Expiry date | Apr 16, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for semiconductor manufacture in which the top corners of conductive features are preferentially etched compared to the etch rate of the vertical and horizontal surfaces, thereby creating a sloped (prograde) profile, i.e., facets. The material removed through the sputter etch process is oxidized and redeposited along the sides of the feature and along the surface of the substrate, thereby improving step coverage when a subsequent dielectric layer is deposited thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.