Method and apparatus for improving data failure rate testing for memory arrays
US5416782A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1992 |
| Grant date | May 16, 1995 |
| Priority date | — |
| Expiry date | Oct 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for testing the data failure rate of a flash memory array comprising apparatus for writing a test pattern to a memory array; and apparatus positioned in a data path prior to the interface between the memory array and circuitry external to the memory array for detecting differences in data read from the memory array and the test pattern written to the memory array, the last mentioned apparatus including apparatus for reading data from the memory array, apparatus for comparing the value of data read from the memory array with the value of data written to the array in the test pattern, and apparatus for storing a indication that a comparison has produced a result indicating a failure to compare.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.